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[VHDL-FPGA-Verilog] usb_device_core

Description: usb 设备 IP核 verilog实现-usb device core, verilog
Platform: | Size: 37888 | Author: 李红敏 | Hits:

[Software Engineering] 8pic_MCU

Description: 8位MCUIP核的设计与应用（verilog IP核设计）PIC处理器 西安电子科技大学硬件工程师培训资料-Design and Application of 8 MCU IP cores (verilog IP core design) PIC processor Xi an University of Electronic Science and Technology Hardware Engineer training materials
Platform: | Size: 11117568 | Author: 崔琦 | Hits:

[VHDL-FPGA-Verilog] fft_core_test

Description: 基于FPGA的FFT的IP核实现，有其详细源码，采用verilog语言编写，内容详细-The FFT based on FPGA IP core implementation, has its source in detail, using verilog language writing, detailed content
Platform: | Size: 8861696 | Author: 赵庆胜 | Hits:

[VHDL-FPGA-Verilog] DDR3_128M16bit_2Port64bit

Description: Xilinx spartan6 DDR3驱动，编程语言Verilog，基于MCB硬核。-Xilinx spartan6 DDR3 driver based on MCB ip core,coding by verilog.
Platform: | Size: 1553408 | Author: 艾顺义 | Hits:

[VHDL-FPGA-Verilog] RAM

Description: 用verilog实现了IP核的使用，例化了一个RAM，用来进行读写操作，另外还编写了斐波那契数列来进行测试。-Using verilog to achieve the use of IP core, the instantiation of a RAM, used to read and write operations, in addition to the preparation of the Fibonacci sequence for testing.
Platform: | Size: 3072 | Author: east | Hits:

[VHDL-FPGA-Verilog] pic10

Description: 本文件夹里面的是实现pic10 CPU的全部verilog代码以及相应的测试脚本代码，当然有一些模块是在quartus中直接编辑波形测试的，所以没有响应的测试脚本文件。 tri_state_port的测试还未完成，test_pic10_status_reg.vt和test_pic10_tri_state_port2.vt都没有完成测试任务 其中有三篇文档： PIC10_RISC_Design.pdf:原文（verilog代码基本都来自原文，对一部分进行了改进），这篇文章写得非常好 PIC10F200_单片机IP核的实现.pdf:对上面的文章结合自己的实验过程进行了翻译和改写，给大家参考 PIC10F:PIC10系列单片机的手册-This folder inside the pic10 CPU is to achieve all the verilog code and the corresponding test script code, of course, there are some modules in quartus directly edit the waveform test, so there is no response to the test script file. Tri_state_port test has not yet completed, test_pic10_status_reg.vt and test_pic10_tri_state_port2.vt are not complete test tasks There are three documents: PIC10_RISC_Design.pdf: the original (verilog code basically the original, on a part of the improvement), this article is written very well PIC10F200_ IP core of the realization of single-chip.pdf: The above article combined with their own experimental process of translation and rewriting, for your reference PIC10F: PIC10 family of microcontrollers
Platform: | Size: 3458048 | Author: Eddie | Hits:

[VHDL-FPGA-Verilog] Buf_FiFo

Description: verilog 编写的FIFO，里边有IP核和控制模块，-verilog write FIFO, inside the IP core and control module,
Platform: | Size: 5120 | Author: 王红伟 | Hits:

[VHDL-FPGA-Verilog] ROM

Description: FPGArom的IP核使用及仿真,Verilog语言，非常详细-IP core and use of simulation FPGArom, Verilog language, very detailed
Platform: | Size: 5943296 | Author: 杨福廷 | Hits:

[VHDL-FPGA-Verilog] zhixinkeji

Description: 北京至芯科技FPGA的学习资料，从备战Quartus II安装到IIC通信协议，每一章都有Verilog代码并且可以实现仿真程序，非常好用，讲的很详细-Beijing Science and Technology FPGA to the core learning materials, preparing to install Quartus II IIC communication protocol, each chapter Verilog code and can achieve simulation program, very easy to use, said very detailed
Platform: | Size: 23173120 | Author: 李浩轩 | Hits:

[VHDL-FPGA-Verilog] ROM

Description: 使用verilog语言实现对altera下cycloneII系列FPGA的片上ROM的创建，读写，调用IP核-Use verilog language to achieve altera under the cycloneII series FPGA on-chip ROM to create, read and write, call IP core
Platform: | Size: 36864 | Author: 张仑仑 | Hits:

[VHDL-FPGA-Verilog] dfe_filter

Description: DEF算法的FIR滤波器verilog代码，内有乘法器IP核，可直接仿真使用-DEF algorithm for FIR filter verilog code with multiplier IP core, can be directly used simulation
Platform: | Size: 2048 | Author: 右下角 | Hits:

[MPI] MY 80c51 IP

Description: verilog和vhdl混写的工程 内含mc8051软核及最小系统 经测试已调通(Verilog and VHDL mixed with the project, including the mc8051 soft core and the smallest system, the test has been transferred)
Platform: | Size: 16939008 | Author: 嘿哟 | Hits:

[VHDL-FPGA-Verilog] modelsim se 10.1a crack

Description: Mentor公司的ModelSim是业界最优秀的HDL语言仿真软件，它能提供友好的仿真环境，是业界唯一的单内核支持VHDL和Verilog混合仿真的仿真器。它采用直接优化的编译技术、Tcl/Tk技术、和单一内核仿真技术，编译仿真速度快，编译的代码与平台无关，便于保护IP核，个性化的图形界面和用户接口，为用户加快调错提供强有力的手段，是FPGA/ASIC设计的首选仿真软件。(Mentor's ModelSim, the industry's best HDL language simulation software, offers a friendly simulation environment and is the industry's only single-core simulator supporting VHDL and Verilog mixed simulations. It uses direct optimization of the compiler technology, Tcl / Tk technology, and a single kernel simulation technology, compile and emulate fast, compiled code has nothing to do with the platform, easy to protect IP core, personalized graphical interface and user interface to speed up the user to debug wrong Provide a powerful means of choice for FPGA / ASIC design simulation software.)
Platform: | Size: 523264 | Author: 冰激凌很牛 | Hits:

[Other] 高大上欧美风商务PPT模板

Description: JPEG_d IP Core Verilog crypted source
Platform: | Size: 15606784 | Author: 发企鹅出去啊 | Hits:

[VHDL-FPGA-Verilog] 8051Core

Description: 8051 Core Verilog RTL IP Code
Platform: | Size: 1597440 | Author: richman | Hits:

[Other] AD多通道采集 FFT实验

Description: FFT核和AD多通道采集的Verilog HDL(Verilog HDL with FFT Core and AD Multichannel Acquisition)
Platform: | Size: 4799488 | Author: xq001 | Hits:

[Other] MIPI_CSI_2_Rx

Description: MIPI CSI 2 Rx verilog / vhdl core
Platform: | Size: 26361856 | Author: suspafar | Hits:

[Other] MIPI_DSI_Tx

Description: MIPI DSI Tx verilog / vhdl core
Platform: | Size: 52234240 | Author: suspafar | Hits:

[VHDL-FPGA-Verilog] 异步FIFO

Description: 纯Verilog实现的异步FIFO，分为读写控制模块，SRAM CORE，同步等几个模块，内含源文件和仿真文件(The asynchronous FIFO implemented by Verilog is divided into read-write control module, SRAM core module and synchronization module)
Platform: | Size: 2048 | Author: wt2110 | Hits:
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